For normal operation of a static random access memory (SRAM) macro that is configured by a vast number of cells, a technology that replaces a defective cell with a redundant cell is known. For example, a cell becomes defective due to foreign particle contamination during manufacturing. A cell also becomes defective due to marginality caused by manufacturing variation, in other words, an insufficient margin for source voltage, temperature, etc., required for operation. For example, a cell does not operate if the source voltage is low.
In the above technology, all cells of 1 word (or 1 column) having a defective cell are replaced with redundant cells of 1 word (or 1 column) (hereinafter, “conventional art 1.” See, for example, Japanese Laid-Open Patent Publication Nos. 2001-67889 and 2003-331597). In the above technology, a redundant cell of 1 column and a read only memory (ROM) that stores position data of a defective cell of 1 bit are provided for each word of a dynamic random access memory (DRAM), and 1 defective cell is replaced with the redundant cell of each word (hereinafter, “conventional art 2.” See, for example, Japanese Laid-Open Patent Publication No. H11-17019).
Recently, however, the source voltage of semiconductor memory has been reduced for lower power consumption, which causes multiple cells to be defective in multiple words and/or in each word due to the marginality.
The conventional art 1 can replace 1 word or 1 column with a redundant word or a redundant column, but cannot if defective cells are in multiple words or multiple columns.
FIG. 36 is a schematic of an example of the conventional art 2. The DRAM cell array depicted in FIG. 36 includes 18 words (rows), 16 bits (columns) of data cells, and 1 column of redundant cells (redundant column). For example, 2 cells indicated by “x” are defective in a specified word. However, only one of the cells can be replaced with the redundant cell, while the other cannot be replaced. As a result, the DRAM becomes defective.
FIG. 37 is a schematic of another example of the conventional art 2. The DRAM cell array depicted in FIG. 37 is that depicted in FIG. 36 to which 1 redundant column is added. To add 1 redundant column, the memory cell array is divided into 2 blocks each of which includes 1 redundant column since data are read from/written into the DRAM cell array in units of bits. If multiple cells are defective in the specified word of the memory cell array on the left, only one of the cells can be replaced with the redundant cell while the other(s) cannot be replaced. As a result, the DRAM becomes defective.